The background art is the CMOS memory cell, where the Pull-up FETs were coupled to the Supply line directly, and the Pull-down FETs were coupled to Ground directly, the advantages of this model were:
1—Every point in a memory cell was a strong point, due to absence of resistive components, so every point inside the memory cell was coupled to either Supply line or Ground via a very low resistance (The FET Drain to Source resistance), this led to high immunity of a memory cell against any interference when used at high operating frequencies.
2—The absence of resistive components in the dynamic current path led to a very fast response during writing process where FETs switch ON and OFF very fast.
The main disadvantage for this model was due to its advantages where the presence of strong points everywhere in the memory cell made the introduction of an external signal to any of those points a trigger for a very high dynamic current which occurs due to the low resistance—Source to Drain resistance of a FET in “On” status—between the Supply/Ground points and the Source of the introduced Input signal.